In the design of integrated circuit devices intended for the processing of digital signals, such as microprocessors, for example, it is sometimes necessary to include an electrically programmable non-volatile memory cell and corresponding decoding circuits in the same integrated circuit. These electrically programmable non-volatile memory cells are known as electrically programmable read only memories EPROMS.
This requirement gives rise to considerable problems in manufacture, and primarily because of the following reason. The processing circuits, or logic circuits for short, are made using low voltage technology. Low voltage technology uses processes for forming devices, particularly MOS transistors, capable of withstanding relative low voltages within a range of 1 to 3 V. Low voltage throughout the application will be indicated by the symbol LV.
In contrast, the decoding circuits of the memories require devices, essentially MOS transistors, capable of operating at relatively high voltages within a range of 7 to 10 V. High voltage throughout the application will be indicated by the symbol HV. This means that the gate dielectrics of the HV devices must have physical characteristics and/or thicknesses which are different from those used in the LV devices. Therefore, the HV devices require special operations for their formation and definition.
In addition, the gate dielectrics of EPROM cells require a thickness which is different from that of the gate dielectrics of the LV devices and the HV devices. The gate dielectrics of EPROM cells also requires specific characteristics to ensure the permanence of the stored data over time.
A prior art process for forming the different types of devices in a single integrated circuit includes the combination of the three specific processes for forming the three types of devices. In other words, this process requires a number of masking operations close to the sum of the masking operations of the three specific processes. However, a process of this kind has a high cost due to both the large number of operations required, and the resulting low yield. The production yield decreases with an increase in a number of operations in the process.
Producing HV circuits together with LV circuits without making use of specific processes for HV devices can be accomplished using a known circuit arrangement in which two or more LV devices, connected in a cascode configuration, are used. However, this approach can be applied advantageously only when the number of HV devices is small. Otherwise, because each HV device is formed from at least two LV devices, the supplementary area required becomes unacceptably large. Moreover, this does not help with the formation of the memory cells. All the specific operations for producing memory cells have to be added to the process in any case.